The storage capacity of solid state drives (SSDs) continues to increase. That is, SSDs are able to support an increasing number of storage units, such as NAND flash memory units. As the storage capacity of SSDs increases, it has become increasingly difficult to scale SSD controllers, which are typically implemented on integrated circuit chips, and which are used to store data to NAND flash memory units and to read data from NAND flash memory units through general-purpose input/output (or GPIO) pins and through chip enable (or CE) pins.
As present-day drive storage devices support an increasing number of NAND flash memory units, (i.e., greater than 2 terabytes of storage capacity), a large number of connections from an SSD controller to the NAND flash memory units of the disk storage device is required. However, allocating additional GPIO and CE pins is disadvantageous, because allocating more pins increases the size of the die package required for manufacturing the SSD controller. Thus, the cost of manufacturing the SSD controller would increase dramatically. Further, laying out an SSD controller integrated circuit comprising additional NAND flash memory pin connections would also be costly and disruptive to current SSD controller manufacturing processes. Hence, it would be advantageous to provide a mechanism whereby existing SSD controllers can support drives that have NAND flash memory capacity in excess of 2 terabytes without allocating additional GPIO or CE pins for connection to a large number of NAND flash memory units.